hrll

everything is broken, even the earth and stone on which you stand

and the project is on paper

my favorite kind of programming project

look,

look at diagrams when you're doing your work

if there's a line connecting the (logical output of - the right side of a block in the diagram) EX and ID, then the registers become available after EX (happens in the same cycle as the MEM stage), meaning that you are able to EXECUTE after EXECUTE - that is, usually in the MEM stage.

however, LOAD (L.D) and STORE (S.D.) instructions never have output available from EXECUTE. Therefore you will need to look for a connection between the logical output of MEM and the input for ID. EXECUTING the instruction dependent on a LOAD will require the EXECUTE to happen after MEM. So it will happen in the WB stage.

When forwarding is available, the CPU contains these lines. When forwarding is not available, the lines come from WB (writeback), meaning that the EXECUTE has to stall and can only begin in the cycle after writeback.

Try drawing these blocks when you are completing a clock cycle diagram on paper - at least for the parts that there are data hazards for. Doing it in a google sheets is harder, but possible.

How to find Data Hazards

Data hazards are when different instructions are handling the same register, and through pipelining, multiple instructions are living in the processor at the same clock cycle. Usually a data hazard is when they are living in different parts of the processor, because you are not allowed to schedule two instructions to do anything in the same unit at the same time.